Liam Kerr
5f09049765
- Correct IRQ number for CLINT timer from 5 to 7 in PLIC and headers. - Add debug prints for MIE, SIE, and MSTATUS CSRs to verify interrupt enablement. - Enable timer (IRQ 7) and global interrupts in MIE/SIE registers. - Update `timer_tick()` to log `mtimecmp` and `mtime` for debugging. - Ensure `stvec` is set and interrupts are properly acknowledged.
23 lines
No EOL
756 B
C
23 lines
No EOL
756 B
C
#ifndef PLIC_H
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#define PLIC_H
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#define PLIC_BASE 0x0c000000UL
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// Priorities: 4 bytes per IRQ (IRQ 0 is reserved/null)
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#define PLIC_PRIORITY(irq) ((volatile uint32_t *)(PLIC_BASE + (irq) * 4))
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// Enables: Each Hart has a 0x80 byte stride for its enable bits
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// For Hart 0 Machine Mode: 0x0c002000
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#define PLIC_ENABLE(hart) ((volatile uint32_t *)(PLIC_BASE + 0x2000 + (hart) * 0x80))
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// Threshold and Claim/Complete: Each Hart has a 0x1000 byte stride
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// For Hart 0 Machine Mode: 0x0c200000 and 0x0c200004
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#define PLIC_THRESHOLD(hart) ((volatile uint32_t *)(PLIC_BASE + 0x200000 + (hart) * 0x1000))
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#define PLIC_CLAIM(hart) ((volatile uint32_t *)(PLIC_BASE + 0x200004 + (hart) * 0x1000))
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#define UART_IRQ 10
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#define TIMER_IRQ 7
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void plic_init();
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#endif |