tehsquidge/SquidgeOS
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5 commits

Author SHA1 Message Date
Liam Kerr
5f09049765 Fix RISC-V timer interrupt (IRQ 7) and enable proper interrupt handling 
- Correct IRQ number for CLINT timer from 5 to 7 in PLIC and headers.
- Add debug prints for MIE, SIE, and MSTATUS CSRs to verify interrupt enablement.
- Enable timer (IRQ 7) and global interrupts in MIE/SIE registers.
- Update `timer_tick()` to log `mtimecmp` and `mtime` for debugging.
- Ensure `stvec` is set and interrupts are properly acknowledged.
 2026-05-02 01:53:03 +01:00
Liam Kerr
ebdd572f8e feat: implement basic timer 2026-05-01 23:14:44 +01:00
Liam Kerr
e3d0c0bab0 (interrupts): clean up PLIC addresses 2026-02-12 02:32:00 +00:00
Liam Kerr
8d5aae1ac9 clean up warnings 2026-02-10 03:01:50 +00:00
Liam Kerr
50757427be Keyboard Work - setting up PLIC, UART, Interrupts 2026-02-10 01:21:49 +00:00