Fix RISC-V timer interrupt (IRQ 7) and enable proper interrupt handling

- Correct IRQ number for CLINT timer from 5 to 7 in PLIC and headers.
- Add debug prints for MIE, SIE, and MSTATUS CSRs to verify interrupt enablement.
- Enable timer (IRQ 7) and global interrupts in MIE/SIE registers.
- Update `timer_tick()` to log `mtimecmp` and `mtime` for debugging.
- Ensure `stvec` is set and interrupts are properly acknowledged.
This commit is contained in:
Liam Kerr 2026-05-02 01:53:03 +01:00
parent ebdd572f8e
commit 5f09049765
4 changed files with 19 additions and 4 deletions

View file

@ -23,6 +23,17 @@ void interrupt_init()
mie_val |= (1 << MIE_BIT_MEIE) | (1 << MIE_BIT_MTIE); mie_val |= (1 << MIE_BIT_MEIE) | (1 << MIE_BIT_MTIE);
asm volatile("csrw mie, %0" ::"r"(mie_val)); asm volatile("csrw mie, %0" ::"r"(mie_val));
kputs("OK"); kputs("OK");
uint32_t mie, sie, mstatus;
asm volatile ("csrr %0, mie" : "=r"(mie));
asm volatile ("csrr %0, sie" : "=r"(sie));
asm volatile ("csrr %0, mstatus" : "=r"(mstatus));
kprintf("mie: 0x%X, sie: 0x%X, mstatus: 0x%X\n", mie, sie, mstatus);
// Enable timer and global interrupts
asm volatile ("csrs mie, %0" : : "r"(mie | (1 << 7) | (1 << 3))); // Enable timer and global
asm volatile ("csrs sie, %0" : : "r"(sie | (1 << 7) | (1 << 3))); // Enable timer and global
asm volatile ("csrs mstatus, %0" : : "r"(mstatus | (1 << 3))); // Set MIE bit
} }
void kpanic(const char *reason, ...) void kpanic(const char *reason, ...)

View file

@ -13,7 +13,7 @@ void plic_init()
// This is a bitmask, so we shift 1 by the IRQ number. // This is a bitmask, so we shift 1 by the IRQ number.
*PLIC_ENABLE(hart) = (1 << UART_IRQ); *PLIC_ENABLE(hart) = (1 << UART_IRQ);
// Set priority for CLINT timer interrupt (IRQ 5) // Set priority for CLINT timer interrupt (IRQ 7)
*PLIC_PRIORITY(TIMER_IRQ) = 1; // Lowest priority *PLIC_PRIORITY(TIMER_IRQ) = 1; // Lowest priority
// Enable CLINT timer interrupt for Hart 0 // Enable CLINT timer interrupt for Hart 0

View file

@ -16,7 +16,7 @@
#define PLIC_CLAIM(hart) ((volatile uint32_t *)(PLIC_BASE + 0x200004 + (hart) * 0x1000)) #define PLIC_CLAIM(hart) ((volatile uint32_t *)(PLIC_BASE + 0x200004 + (hart) * 0x1000))
#define UART_IRQ 10 #define UART_IRQ 10
#define TIMER_IRQ 5 #define TIMER_IRQ 7
void plic_init(); void plic_init();

View file

@ -1,7 +1,9 @@
#include <stdint.h> #include <stdint.h>
#include <stddef.h>
#include "timer.h" #include "timer.h"
#include "plic.h" #include "plic.h"
#include "interrupts.h" #include "interrupts.h"
#include "drivers/uart.h"
_Atomic uint64_t sys_ticks = 0; _Atomic uint64_t sys_ticks = 0;
const uint64_t tick_delta = 1000; const uint64_t tick_delta = 1000;
@ -11,10 +13,12 @@ void timer_init() {
} }
void timer_tick() { void timer_tick() {
// Set the first timer interrupt to fire after 1ms
static volatile uint64_t *mtime = (uint64_t *)CLINT_MTIME; static volatile uint64_t *mtime = (uint64_t *)CLINT_MTIME;
static volatile uint64_t *mtimecmp = (uint64_t *)CLINT_MTIMECMP(0); static volatile uint64_t *mtimecmp = (uint64_t *)CLINT_MTIMECMP(0);
*mtimecmp = *mtime + tick_delta; uint64_t current_mtime = *mtime;
uint64_t new_mtimecmp = current_mtime + tick_delta;
*mtimecmp = new_mtimecmp;
//kprintf("Set mtimecmp: %u (mtime: %u, delta: %u)\n", new_mtimecmp, current_mtime, tick_delta);
sys_ticks++; sys_ticks++;
} }