Fix RISC-V timer interrupt (IRQ 7) and enable proper interrupt handling

- Correct IRQ number for CLINT timer from 5 to 7 in PLIC and headers.
- Add debug prints for MIE, SIE, and MSTATUS CSRs to verify interrupt enablement.
- Enable timer (IRQ 7) and global interrupts in MIE/SIE registers.
- Update `timer_tick()` to log `mtimecmp` and `mtime` for debugging.
- Ensure `stvec` is set and interrupts are properly acknowledged.

src/kernel/plic.h

@@ -16,7 +16,7 @@
 #define PLIC_CLAIM(hart) ((volatile uint32_t *)(PLIC_BASE + 0x200004 + (hart) * 0x1000))
 
 #define UART_IRQ 10
-#define TIMER_IRQ 5
+#define TIMER_IRQ 7
 
 void plic_init();