124 lines
No EOL
3.1 KiB
C
124 lines
No EOL
3.1 KiB
C
#include <stddef.h>
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#include <stdint.h>
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#include <stdarg.h>
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#include <drivers/uart.h>
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#include <syscon/syscon.h>
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#include <kernel/plic.h>
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#include <kernel/interrupts.h>
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#include <kernel/memory.h>
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void interrupt_init()
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{
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kprint("Initialising Interrupts...");
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uint64_t mstatus_val;
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asm volatile("csrr %0, mstatus" : "=r"(mstatus_val));
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mstatus_val |= (1 << MSTATUS_BIT_MIE);
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asm volatile("csrw mstatus, %0" ::"r"(mstatus_val));
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uint64_t mie_val;
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asm volatile("csrr %0, mie" : "=r"(mie_val));
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mie_val |= (1 << MIE_BIT_MEIE); //|(1 << MIE_BIT_MTIE);
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asm volatile("csrw mie, %0" ::"r"(mie_val));
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kputs("OK");
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}
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void kpanic(const char *reason, ...)
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{
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va_list args;
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va_start(args, reason);
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kputs("\n!!! PANIC !!!\n");
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kprintf_internal(reason, args);
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kputs("\n!!! PANIC !!!\n");
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va_end(args);
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poweroff();
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}
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void kpanic_force()
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{
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kprint("\n!!! FORCE PANIC !!!\n");
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// 'ebreak' is the standard RISC-V way to trigger a debug trap.
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__asm__ volatile("ebreak");
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kprint("Force panic falled. Power off. \n");
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poweroff();
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kprint("Force panic falled. Power off failed. sleep until interupt. \n");
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while (1)
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{
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__asm__ volatile("wfi");
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}
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}
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void handle_trap()
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{
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// Read the 'mcause' register to see WHY we trapped
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unsigned long cause;
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__asm__ volatile("csrr %0, mcause" : "=r"(cause));
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// Check if the top bit is 1 (Interrupt) or 0 (Exception)
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// For 64-bit RISC-V, the bit is 63
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int is_interrupt = (cause >> 63) & 1;
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if (is_interrupt)
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{
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unsigned long code = cause & 0xfff;
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handle_interrupt(code);
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return;
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}
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else
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{
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// fault address (if applicable)
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uintptr_t mtval;
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asm volatile("csrr %0, mtval" : "=r"(mtval));
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kprintf("Faulting Address (if applicable): %x\n", mtval);
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switch (cause)
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{
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case 0:
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kpanic("Reason: Instruction Address Misaligned\n");
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break;
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case 1:
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kpanic("Reason: Instruction Access Fault\n");
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break;
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case 2:
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kpanic("Reason: Illegal Instruction\n");
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break;
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case 3:
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kpanic("Reason: Breakpoint (ebreak)\n");
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break;
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case 4:
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kpanic("Reason: Load Address Misaligned\n");
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break;
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case 5:
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kpanic("Reason: Load Access Fault\n");
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break;
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case 6:
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kpanic("Reason: Store/AMO Address Misaligned\n");
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break;
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case 7:
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kpanic("Reason: Store/AMO Access Fault\n");
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break;
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default:
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kpanic("Reason: Unknown Exception Code %d\n", cause);
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break;
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}
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}
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}
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void handle_interrupt(unsigned long code)
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{
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switch (code)
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{
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case 7:
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break; // timer Interrupt. Ignoring for now.
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case 11:
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volatile uint32_t *claim_reg = (uint32_t *)PLIC_CLAIM_COMPLETE;
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uint32_t irq = *claim_reg;
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if (irq == 10)
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{
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uart_handle_interrupt();
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}
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*claim_reg = irq;
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break;
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}
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} |