memory testing and robustness

This commit is contained in:
Liam Kerr 2026-02-09 03:28:54 +00:00
parent 2296179bf8
commit 9f833ca32c
4 changed files with 95 additions and 9 deletions

View file

@ -32,6 +32,10 @@ void handle_trap() {
unsigned long cause;
__asm__ volatile("csrr %0, mcause" : "=r"(cause));
// fault address (if applicable)
uintptr_t mtval;
asm volatile("csrr %0, mtval" : "=r"(mtval));
switch(cause) {
case 0: kprint("Reason: Instruction Address Misaligned\n"); break;
case 1: kprint("Reason: Instruction Access Fault\n"); break;
@ -44,6 +48,7 @@ void handle_trap() {
default:
kprintf("Reason: Unknown Exception Code %d\n", cause);
}
kprintf("Faulting Address (if applicable): 0x%p\n", mtval);
poweroff();
}