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(interrupts): Timer interrupts enabled and handled

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This commit is contained in:
Liam Kerr 2026-02-14 17:21:48 +00:00
parent 665be11c76
commit 44427f7734
3 changed files with 17 additions and 14 deletions
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9
src/kernel/interrupts.c
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@ -11,13 +11,14 @@ void interrupt_init()
{
kprint("Initialising Interrupts...");
uint64_t mstatus_val;
asm volatile("csrr %0, mstatus" : "=r"(mstatus_val));
mstatus_val |= (1 << MSTATUS_BIT_MIE);
asm volatile("csrw mstatus, %0" ::"r"(mstatus_val));
uint64_t mie_val;
asm volatile("csrr %0, mie" : "=r"(mie_val));
mie_val |= (1 << MIE_BIT_MEIE); //|(1 << MIE_BIT_MTIE);
mie_val |= (1 << MIE_BIT_MEIE) | (1 << MIE_BIT_MTIE);
asm volatile("csrw mie, %0" ::"r"(mie_val));
kputs("OK");
}
@ -114,7 +115,11 @@ void handle_interrupt(unsigned long code)
switch (code)
{
case 7:
break; // timer Interrupt. Ignoring for now.
static volatile uint64_t *mtime = (uint64_t *)CLINT_MTIME;
static volatile uint64_t *mtimecmp = (uint64_t *)CLINT_MTIMECMP(0);
*mtimecmp = *mtime + 100000;
break;
case 11:
volatile uint32_t *claim_reg = (uint32_t *)PLIC_CLAIM(0);
uint32_t irq = *claim_reg;

10
src/kernel/interrupts.h
View file

@ -1,6 +1,16 @@
#ifndef PANIC_H
#define PANIC_H
#define MSTATUS 0x300
#define MIE 0x304
#define MSTATUS_BIT_MIE 3
#define MIE_BIT_MTIE 7
#define MIE_BIT_MEIE 11
#define CLINT_BASE 0x02000000UL
#define CLINT_MTIME (CLINT_BASE + 0xBFF8UL)
#define CLINT_MTIMECMP(h) (CLINT_BASE + 0x4000UL + (8UL * (h)))
// This should match the order of registers in traps.S
typedef struct {

12
src/syscon/syscon.h
View file

@ -8,18 +8,6 @@
#define SYSCON_POWEROFF 0x5555
#define SYSCON_REBOOT 0x7777
#define write_register(register, value) \
asm volatile("csrrw zero, %0, %1" ::"i"(register), "r"(value))
#define read_register(register, destination) \
asm volatile("csrrs %0, %1, zero" : "=r"(destination) : "i"(register))
#define MSTATUS 0x300
#define MIE 0x304
#define MSTATUS_BIT_MIE 3
#define MIE_BIT_MTIE 7
#define MIE_BIT_MEIE 11
void poweroff(void);
void reboot(void);