(interrupts): Timer interrupts enabled and handled
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parent
665be11c76
commit
44427f7734
3 changed files with 17 additions and 14 deletions
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@ -11,13 +11,14 @@ void interrupt_init()
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{
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{
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kprint("Initialising Interrupts...");
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kprint("Initialising Interrupts...");
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uint64_t mstatus_val;
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uint64_t mstatus_val;
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asm volatile("csrr %0, mstatus" : "=r"(mstatus_val));
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asm volatile("csrr %0, mstatus" : "=r"(mstatus_val));
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mstatus_val |= (1 << MSTATUS_BIT_MIE);
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mstatus_val |= (1 << MSTATUS_BIT_MIE);
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asm volatile("csrw mstatus, %0" ::"r"(mstatus_val));
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asm volatile("csrw mstatus, %0" ::"r"(mstatus_val));
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uint64_t mie_val;
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uint64_t mie_val;
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asm volatile("csrr %0, mie" : "=r"(mie_val));
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asm volatile("csrr %0, mie" : "=r"(mie_val));
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mie_val |= (1 << MIE_BIT_MEIE); //|(1 << MIE_BIT_MTIE);
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mie_val |= (1 << MIE_BIT_MEIE) | (1 << MIE_BIT_MTIE);
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asm volatile("csrw mie, %0" ::"r"(mie_val));
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asm volatile("csrw mie, %0" ::"r"(mie_val));
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kputs("OK");
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kputs("OK");
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}
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}
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@ -114,7 +115,11 @@ void handle_interrupt(unsigned long code)
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switch (code)
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switch (code)
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{
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{
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case 7:
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case 7:
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break; // timer Interrupt. Ignoring for now.
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static volatile uint64_t *mtime = (uint64_t *)CLINT_MTIME;
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static volatile uint64_t *mtimecmp = (uint64_t *)CLINT_MTIMECMP(0);
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*mtimecmp = *mtime + 100000;
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break;
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case 11:
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case 11:
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volatile uint32_t *claim_reg = (uint32_t *)PLIC_CLAIM(0);
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volatile uint32_t *claim_reg = (uint32_t *)PLIC_CLAIM(0);
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uint32_t irq = *claim_reg;
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uint32_t irq = *claim_reg;
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@ -1,6 +1,16 @@
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#ifndef PANIC_H
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#ifndef PANIC_H
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#define PANIC_H
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#define PANIC_H
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#define MSTATUS 0x300
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#define MIE 0x304
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#define MSTATUS_BIT_MIE 3
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#define MIE_BIT_MTIE 7
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#define MIE_BIT_MEIE 11
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#define CLINT_BASE 0x02000000UL
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#define CLINT_MTIME (CLINT_BASE + 0xBFF8UL)
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#define CLINT_MTIMECMP(h) (CLINT_BASE + 0x4000UL + (8UL * (h)))
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// This should match the order of registers in traps.S
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// This should match the order of registers in traps.S
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typedef struct {
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typedef struct {
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@ -8,18 +8,6 @@
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#define SYSCON_POWEROFF 0x5555
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#define SYSCON_POWEROFF 0x5555
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#define SYSCON_REBOOT 0x7777
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#define SYSCON_REBOOT 0x7777
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#define write_register(register, value) \
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asm volatile("csrrw zero, %0, %1" ::"i"(register), "r"(value))
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#define read_register(register, destination) \
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asm volatile("csrrs %0, %1, zero" : "=r"(destination) : "i"(register))
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#define MSTATUS 0x300
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#define MIE 0x304
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#define MSTATUS_BIT_MIE 3
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#define MIE_BIT_MTIE 7
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#define MIE_BIT_MEIE 11
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void poweroff(void);
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void poweroff(void);
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void reboot(void);
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void reboot(void);
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