83 lines
1.6 KiB
ArmAsm
83 lines
1.6 KiB
ArmAsm
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# traps.S
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.section .text
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.align 4 # mtvec requires 4-byte alignment
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.global trap_entry
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trap_entry:
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# 1. Create space on the stack for 32 registers (32 * 8 = 256 bytes)
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addi sp, sp, -256
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# 2. Save all General Purpose Registers (GPRs)
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# We don't save x0 (zero) because it's always zero
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sd ra, 0(sp)
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sd gp, 8(sp)
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sd tp, 16(sp)
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sd t0, 24(sp)
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sd t1, 32(sp)
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sd t2, 40(sp)
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sd s0, 48(sp)
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sd s1, 56(sp)
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sd a0, 64(sp)
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sd a1, 72(sp)
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sd a2, 80(sp)
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sd a3, 88(sp)
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sd a4, 96(sp)
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sd a5, 104(sp)
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sd a6, 112(sp)
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sd a7, 120(sp)
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sd s2, 128(sp)
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sd s3, 136(sp)
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sd s4, 144(sp)
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sd s5, 152(sp)
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sd s6, 160(sp)
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sd s7, 168(sp)
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sd s8, 176(sp)
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sd s9, 184(sp)
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sd s10, 192(sp)
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sd s11, 200(sp)
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sd t3, 208(sp)
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sd t4, 216(sp)
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sd t5, 224(sp)
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sd t6, 232(sp)
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# 3. Call your C handler
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# The CPU already put the cause in 'mcause', so C can read it
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call handle_trap
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# 4. Restore all GPRs
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ld ra, 0(sp)
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ld gp, 8(sp)
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ld tp, 16(sp)
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ld t0, 24(sp)
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ld t1, 32(sp)
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ld t2, 40(sp)
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ld s0, 48(sp)
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ld s1, 56(sp)
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ld a0, 64(sp)
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ld a1, 72(sp)
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ld a2, 80(sp)
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ld a3, 88(sp)
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ld a4, 96(sp)
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ld a5, 104(sp)
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ld a6, 112(sp)
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ld a7, 120(sp)
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ld s2, 128(sp)
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ld s3, 136(sp)
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ld s4, 144(sp)
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ld s5, 152(sp)
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ld s6, 160(sp)
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ld s7, 168(sp)
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ld s8, 176(sp)
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ld s9, 184(sp)
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ld s10, 192(sp)
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ld s11, 200(sp)
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ld t3, 208(sp)
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ld t4, 216(sp)
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ld t5, 224(sp)
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ld t6, 232(sp)
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# 5. Shrink the stack back
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addi sp, sp, 256
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# 6. Return from Machine-mode trap
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mret
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